Increasing bit resolution in digital imaging applications for navigation (such as in capacitive touch screen integrated controllers, or in integrated optical imagers in OFN/mice) generally requires that steps be taken during the design phase to address problems arising from mismatches between integrated components in ADCs. Pipeline ADC architecture is frequently used in imaging applications because of its ability to simultaneously process multiple elements in imaging data arrays. In metal oxide silicon (MOS) pipeline ADCs and the integrated circuits into which they are incorporated, the most critical components to match are often the capacitors in the multiplication digital-to-analog converters (DACs) of each pipeline element. Capacitors, and especially large capacitors, can require large amounts of area on an integrated circuit, and may be difficult to design and implement when the effective number of bits (ENOB) in the ADC equals or exceeds 12. In addition, large capacitors can significantly increase the amount of power consumed by the ADC.
Numerous error calibration techniques have therefore been proposed with the aim of achieving high ENOB while not consuming excessive integrated circuit real estate and ADC power. Radix digital calibration techniques typically require substantial digital manipulation and prolonged reiterations during digital calibration. Averaging active and passive analog capacitors is another technique that has been used to increase the ENOB of pipeline ADCs, but which typically requires extra amplifiers and/or extra capacitors. In addition, an averaging clock phase, in addition to normal clock operations, is also typically required. These requirements add to integrated circuit size, complexity and design, and also increase the ADC power consumption.
Some publications discussing the foregoing problems include, but are not limited to: P. Rombouts et al., IEEE Transactions on Circuits and Systems, V.45, N9, September 1998; El-Sankary et al., IEEE Transactions on Circuits and Systems, V.51, N10, October 2004; Sean Chang, et. al., IEEE Journal of Solid State Circuits, V.37, N6, June 2002; Stephen H. Lewis, et. al., IEEE Journal of Solid State Circuits, V.27, N3, March 1992; John P. Keane, et. al., IEEE Journal on Circuits and Systems, V.52, N1, January 2005; O. Bernal, et al., IMTC 2006 Technology Conference, Sorrento, Italy, Apr. 24-27, 2006; Ion P. Opris, et. al., IEEE Journal of Solid State Circuits, V.33, N12, December 1998; Dong-Young Chang, et. al., IEEE Transactions on Circuits and Systems, V.51, N11, November 2004; Yun Chiu, et. al., IEEE Journal of Solid State Circuits, V.39, N12, December 2004, and Hsin-Shu Chen, IEEE Journal of Solid State Circuits, V.36, N6, June 2001. Each of the foregoing references is hereby incorporated by reference herein, each in its respective entirety.
What is needed is a pipeline ADC featuring reduced capacitor mismatch errors, smaller capacitors, and lower ADC power consumption